In this module we will study automatic test pattern generation (ATPG) using sensitization–propagation -justification approach. We will first introduce the basics of. 1. VLSI Design Verification and Testing. Combinational ATPG Basics. Mohammad Tehranipoor. Electrical and Computer Engineering. University of Connecticut. Boolean level. • Classical ATPG algorithms reach their limits. ➢ There is a need for more efficient ATPG tools! 6. Circuits. • Basic gates. – AND, OR, EXOR, NOT.

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Automatic test pattern generation

Views Read Edit View history. A short circuit between two signal lines is called bridging faults. At transistor level, a transistor maybe stuck-short or stuck-open. Also, due to the presence of memory elements, the controllability and observability of the internal signals in a sequential circuit are in general much more difficult than those in a combinational logic circuit.

In such a circuit, any single fault will be inherently undetectable. The output of a test pattern, when testing a fault-free device that works exactly as designed, is called the expected output of that test pattern. The stuck-at fault model is a logical fault model because no delay information is associated with the fault definition.

The classic example of this is a redundant circuit, designed such that no single fault causes the output to change. The ATPG process for a targeted fault consists of two phases: First, the fault may be intrinsically undetectable, such that no patterns exist that can detect that particular fault.

For designs that are sensitive to area or performance overhead, the solution of using sequential-circuit ATPG and partial scan offers an attractive alternative to the popular full-scan solution, which is based on combinational-circuit ATPG. For nanometer technology, many current design validation problems are becoming manufacturing test problems as well, so new fault-modeling and ATPG techniques will be needed.

Therefore, many different ATPG methods have been developed to address combinational and sequential circuits. Hence, if a circuit has n signal lines, there are potentially 2n stuck-at faults defined on the circuit, of which some can be viewed as being equivalent to others.


Even a simple stuck-at fault requires a sequence of vectors for detection in a sequential circuit.

Sequential-circuit ATPG searches for a sequence of test vectors to detect a particular fault through the space of all possible test vector sequences. It is also called a permanent fault model because the faulty effect is assumed to be permanent, in contrast to vasics faults which occur seemingly at random and transient faults which occur sporadically, perhaps depending on operating conditions e.

In the latter case, dominant driver keeps its value, while the other one gets the AND or OR value of its own and the dominant driver. ATPG efficiency is another important consideration that is influenced by the fault model under consideration, the type of circuit under test full scansynchronous sequential, or asynchronous sequentialthe level of abstraction used to represent the circuit under test gate, register-transfer, switchand the required test quality.

The logic values observed at the device’s primary outputs, while applying a test pattern to some device under test DUTare called the output of that test pattern. Various search strategies and heuristics have been devised to find a shorter sequence, or to find a sequence faster. Fault propagation moves the resulting signal value, or fault effect, forward by sensitizing a path from the fault site to a primary output.

Equivalent faults produce the same faulty behavior for all input patterns. Fault activation establishes a signal value at the fault model site that is opposite of the value produced by the fault model.

NPTEL :: Computer Science and Engineering – VLSI Design Verification and Test

This allows using a relatively simple vector matrix to quickly test all the comprising FFs, as well as to trace failures to specific FFs.

This page was last edited on 23 Novemberat During design validation, engineers can no longer ignore the effects of crosstalk and power supply noise on reliability and performance. The effectiveness of ATPG is measured by the number absics modeled defects, or fault modelsdetectable and by the number of generated patterns.

However, according to reported results, no single strategy or heuristic out-performs others for all applications or circuits. The single stuck-at fault model is structural because it is defined based on a structural gate-level circuit model. Atp using this site, you agree to the Terms of Use and Privacy Policy. During test, a so-called scan-mode is enabled forcing all flip-flops FFs to be connected in a simplified fashion, bascis bypassing their interconnections as intended during normal operation.


Retrieved from ” https: ATPG is a topic that is covered by several conferences throughout the year.

Combinational ATPG Basics

Any single fault from the set of equivalent faults can represent the whole set. However, these test generators, combined with low-overhead DFT techniques such as partial scanhave shown a certain degree of success in testing large designs.

These metrics generally indicate test quality higher with more fault detections and test application time higher with more patterns. This observation implies that a test generator should include a comprehensive set of heuristics. In the past several decades, the most popular fault model used in practice is the single stuck-at fault model.

The combinational ATPG method allows testing the individual nodes or flip-flops of the logic circuit without being concerned with the operation of the overall circuit.

In this model, one of the signal lines in a circuit is assumed to be stuck at a fixed logic value, regardless of what inputs are supplied to the circuit. In stuck-short, a transistor behaves as it is always conducts or stuck-onand stuck-open is when a transistor never conducts current or stuck-off.

This model is used to describe faults for CMOS logic gates. ATPG can fail to find a test for a particular fault in at least two cases. Bridging to VDD or Vss is equivalent to stuck at fault model.

Second, it is possible that a detection pattern exists, but the algorithm cannot find one. From Wikipedia, the free encyclopedia.

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